A basic building block of many digital and mixed-signal systems is a regenerative latch circuit. A regenerative latch is a circuit that can receive a relatively weak input signal and regeneratively amplify the input signal to full-amplitude logic levels. The speed and sensitivity of this type of latch circuit are operating parameters that typically have a large influence on the performance of the overall system. For instance, when a latch is used as a decision-making circuit in a high-speed (e.g., multi-Gbit/s) serial link receiver, the maximum operating frequency of the latch may determine the highest data rate that can be supported by the receiver. If the pulses arriving at the receiver have been attenuated and distorted by high-frequency losses in the transmission media, a latch with high input sensitivity may be needed to recover the data bits with a low bit error rate (BER).
Another application in which a high-speed latch with good input sensitivity is needed is high-performance analog-to-digital conversion, in which the latch is used as a voltage comparator (1-bit quantizer). A fast comparator is needed in many analog-to-digital converter (ADC) architectures designed for high sampling rates (e.g., >1 G samples/second), and the sensitivity of the comparator should be high so that the ADC resolution is not degraded, usually characterized as the effective number of bits (ENOB).